The present invention relates to a shift register circuit.
A shift register circuit has been used for a scanning portion of a sample hold circuit to which is inputted video signals and which holds samples of about 60 bits.
A conventional shift register circuit of this kind generally comprises a first latch portion in which one terminal of a transfer gate is connected to an input terminal, another terminal thereof is connected to an input terminal of an inverter which is connected in anti-parallel with a clocked inverter, and an output terminal of the inverter is connected to a first cascade output terminal, and a second latch portion which has the same configuration as the first latch portion but in which clock signals inputted to a transfer gate and to a clocked inverter are anti-phase to clock signals inputted to those in the first latch portion, the first latch portion and the second latch portion being cascade-connected.
The conventional shift register circuit mentioned above uses two latch circuits per bit thereby increasing the number of elements required in the circuit. Also, in such a conventional circuit, a change of each bit value synchronizes with each rising timing of the clock signal and, therefore, one shift register having two latch portions can generate only one bit output, resulting in a slow shifting speed. Further, there exists a transient period wherein output signals by the bits neighboring to each other become an intermediate value which is not a "H" level nor a "L" level, which causes malfunction of the circuit.